(1) Field of the Invention
The present invention relates to a BIST (Built-in Self Test) for a semiconductor integrated circuit, and particularly to a technique to test an SRAM at high speed by the BIST.
(2) Description of the Related Art
In recent years, a high-integration technique, such as a SoC by which a plurality of processors, a programmable logic circuit, dedicated hardware, a plurality of memories and so on are mounted, has been put into practical use. Due to such high integration, the number of external input/output terminals is comparatively small for its circuit size, and it is difficult to conduct a sufficient test for the semiconductor integrated circuit from outside. Therefore, to test the quality of memory circuits incorporated in the semiconductor integrated circuit, a BIST which uses only the circuits incorporated in the semiconductor integrated circuit is often applied.
However, it is necessary for the BIST to provide a circuit block only for the test, and this causes an area overhead on the circuit.
To reduce such an area overhead, Japanese Laid-open Patent Application Publication No. 2000-111618 (Document 1) discloses a technique to share a BIST circuit that generates a test vector, to test a plurality of SRAMs.
However, with the structure disclosed by the Document 1, since the BIST circuit provides a plurality of SRAMs with a test vector, the length of a wire led to an SRAM placed away from the BIST circuit is long, and an interconnect delay becomes large.
If the interconnect delay is relatively large with respect to the operation speed of the SRAM, the BIST circuit is required to provide a test vector in accordance with the SRAM whose interconnect delay is large. Therefore, the test speed is limited to the interconnect delay speed, and it is impossible to conduct a test at an original speed of the memory circuit, that is, so called an at-speed test. This is a problem.